address bus

Large data capacity. Two level FLASH is combined with same data and address bus.

大容量数据存储：采用两级Flash存储器组合使用，利用相同的数据、地址总线统一寻址。

The irredundant sorting bus encoding method reduces the power dissipation of highly capacitive memory address bus based on the dynamic reordering of the modified offset address bus lines.

提出了一种新的低功耗非冗余排序总线编码方法，通过对改进的偏移地址线的动态重排以降低具有高负载的地址总线的功耗。

The microprocessor uses the address bus to locate data stored in memory.

微处理机使用地址总线设定在存贮器中存贮的数据的地址。

By the idea of computer bus, system realizes the multichannel input data collection by multipleuse address bus.

系统基于总线设计思路，利用地址复用功能简单方便地实现对多通道输入数据的采集。

By means of this method the Crosstalk faults of address bus, data bus and control bus in a SoC chip can be tested. The result also show that the area overhead is also decreased drastically compared with other method.

利用该方法，SoC芯片中地址、数据和控制总线的串扰故障均得到了测试，实验结果也表明其硬件开销较其它方案大大降低。

Address Bus: Locates data stores in the memory, input port, or output port.

地址总线: 确定数据在存储器, 输入口或输出口中的存储位置.

Multiplexed address& data bus

多路传送地址与数据总线

What is the uP data and address bus width?

微处理器的数据总线和地址总线的带宽分别为多少？

In monitoring and control system of the simulator, the SCM system is defined as including: frequency oscillator, watchdog and EEPROM, RS232 interface, the CPU data bus and address bus driver latch.

在模拟器测控系统中，把单片机系统定义为包括：主频振荡器、看门狗和EEPROM、RS232接口、CPU、数据总线驱动器和地址总线锁存器。

The parallel print ports of IBM-PC can be extended to three bi-directional 8-bit I/ O ports by a programmable integrated circuit chip named 8255. The three I/ O ports can be used as data bus, address bus and control bus of the data-acquisition instrument.

通过可编程并行接口芯片8255将IBM Pc并行打印端口扩展成3个具有双向通讯功能的8位I/O端口，利用这3个I/O端口分别作为数据采集仪器的数据总线、地址总线和控制总线。

The actual address that is placed on the address bus when accessing a memory location or register.

当访问内存位置或寄存器时，在地址总线上的真实的地址。

The address bus is used by the processor to select aspecific memory location or register within a particular peripheral.

地址总线被处理器用来选择在特定外设中的存储器地址或寄存器。

A memory map is the addressing plan for the address bus bits.

存贮器布局就是地址总线各位的寻址平面图.

This kind of interface provides 8-bit bidirectional communication, has data/ address bus, control bus and status bus, and responds to the requirement of interruption. It almost has the features of microcomputer bus and makes the design feasible theoretically.

并行接口在EPP模式下能实现8位数据的双向传输，具有数据/地址线、控制线和状态线，能响应中断请求，已初步具有总线的接口特性，为开发平台的实现提供了基础。

It will become the basis of Shared Bus. Though the analysis about the PowerPC Bus, there are four parts in BIU: Instruction Pretreatment Part, Address Bus Treatment Part, Data Bus Treatment Part and Data Pos-treatment Part.

通过对PowerPC结构的总线协议的分析，总线接口部分主要由指令预处理部分、地址总线处理部分、数据总线处理部分和数据后处理部分组成，完成微处理器和外部总线的数据交互。

The power dissipated by the address bus is the important power dissipation source of the DSP.

地址总线的功耗是DSP功耗的重要来源.

The address bus specifies the memory locations ( addresses ) for the data transfers.

地址总线为数据传输指明内存位置 ( 地址 ).

The address bus specifies the memory locations ( addresses) for the data transfers.

地址总线为数据传输指明内存位置（地址）。

The system bus is divided into three logical functions; the address bus, the data bus and the control bus.

系统总线的功能在逻辑上被划分为三部分：地址总线、数据总线和控制总线。

During the analysis of system simulation, the address bus, the data bus and the write/ read signals are explained in detail.

在系统仿真分析中，对地址总线、数据总线以及读写信号进行了详细的说明。

The paper also discusses lots of circuit in data acquisition system, just like A/ D convert circuit, logic control circuit, address bus circuit, data-storage circuit and communication interface etc.

本文对数据采集系统中诸如模数转换电路、逻辑控制电路、地址产生电路、数据存储及通信接口电路等关键技术都进行了阐述。

The memory system of dual channel A/ D automatic acquisition is studied in this paper. Using transceivers and gating controllers, the data bus and address bus of RAM are respectively controlled.

本文研究了双通道A/D自动采集存储系统，利用数据收发器及数据选通控制器分别控制RAM的数据线及地址控制线。

The interface adopts 16-bit-wide data bus, 10-bit-wide address bus and provides information by non-DMA mode.

该接口采用16位数据线，10位地址线，并以非DMA方式提供信息。

A novel adaptive-offset bus encoding method was presented for reducing the power dissipation of highly capacitive memory address bus.

为了降低大负载地址总线的功耗，提出了一种新的低功耗自适应偏移量总线编码方法。

The system controlling logic, multiplexing data bus and multiplexing address bus have been designed. The simulations have passed.

完成了系统的控制逻辑、数据总线复用和解码部分的地址复用器的设计，仿真并通过。

The AO line is usually tied to the least significant bit of the address bus.

AO线通常被连结到地址总线的最低有效位。

A 32 bit address bus can locate 4 Gigas ( 2 ^ 32 ) of different memory locations.

32位地址总线可以确定4G ( 2的32次幂 ) 个不同的存储位置.

DMA controller has dedicated on-chip address bus and data bus for DMA transfers, which are controlled DMA register.

DMA有专用的片内地址和数据总线，所有DMA访问都通过DMA的专用总线，并且由DMA控制器控制。